After integrated circuits are produced, it is desirable to be able to test those integrated circuits for proper function so that malfunctioning integrated circuits can be removed and production yield can be determined. This is typically performed using a test apparatus that connects to pins or pads of the integrated circuit, provides power to the integrated circuit, and causes entry of the integrated circuit into a desired one of its test modes.
While this approach is suitable in some circumstances, issues may arise. For example, out of a desire to utilize a single voltage stack for test mode entry and during test modes, all voltage monitors except those for a minimum voltage for test detection and power on reset are masked, which may allow proper operation during test modes, but during test mode entry, analog intellectual property packages (IPs) within the integrated circuit may be operated outside of their rated operating voltages which may result in failure to enter test mode, ultimately resulting in yield loss. As another example, yielding to a desire to reduce the number of pins or pads used by the integrated circuit for testing and to reduce the number probes used by the tester to electrically connect to those pins or pads may result in excess power consumption and potential shortening of the life of the integrated circuit. Another result of prior art setups may result in repeated reset if any voltage drop occurs when supply voltage is ramping up during boot, which may in turn cause a delay in the start of applications when the device is used in customer or end user environment (e.g. a device fitted in a car).
Existing designs that aim to eliminate this issue are “workarounds” at best and create unnecessary device constraints, such as a delay in bootup time, consumption of additional area on the integrated circuit, excess power consumption, and the addition of an extra pin or pad and probe and resulting cost increases. Therefore, further development into this area is needed.